Integrated MEMS and CMOS package and method
US8395252B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 12, 2010 |
| Grant date | Mar 12, 2013 |
| Priority date | — |
| Expiry date | Nov 12, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1461
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
An apparatus for packaging MEMS and ICs can include a semiconductor substrate, one or more MEMS devices, an enclosure, and one or more bonding structures. The semiconductor substrate can be bonded to a portion of the surface region. The semiconductor substrate can include one or more integrated circuits. Also, the semiconductor substrate can have an upper surface region. The one or more MEMS devise can overlie an inner region of the upper surface region formed by the semiconductor substrate. The enclosure can house the one or more MEMS devices. The enclosure can overlie a first outer region of the upper surface region. Also, the enclosure can have an upper cover region. The one or more bonding structures can be provided within a second outer region of the supper surface region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.