Patent · US Active

Homogeneous dual-rail logic for DPA attack resistive secure circuit design

US8395408B2 · kind B2 · utility

6Cited by

0References

19Claims

0Family size

Assignee

The Regents of the University of California · US

Inventors

Kazuyuki Tanimura · Irvine, US
Nikil Dutt · Irvine, US

Key dates

Filing date	Oct 31, 2011
Grant date	Mar 12, 2013
Priority date	—
Expiry date	Oct 31, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/096
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Homogenous dual-rail logic for DPA attack resistive secure circuit design is disclosed. According to one embodiment, an HDRL circuit comprises a primary cell and a complementary cell, wherein the complementary cell is an identical duplicate of the primary cell. The HDRL circuit comprises a first set of inputs and a second set of inputs, wherein the second set of inputs are a negation of the first set of inputs. The HDRL circuit has a differential power at a level that is resistive to DPA attacks.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.