Low power and low spur sampling PLL
US8395427B1 · kind B1 · utility
8Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2010 |
| Grant date | Mar 12, 2013 |
| Priority date | — |
| Expiry date | Jul 3, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/091
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Control circuitry and method of controlling for a sampling phase lock loop (PLL). By controlling the duty cycle of one or more sampling control signals, power consumption by the reference signal buffer and spurious output signals from the sampling PLL being controlled can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.