Digital phase locking loop and method for eliminating glitches
US8395430B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 18, 2011 |
| Grant date | Mar 12, 2013 |
| Priority date | — |
| Expiry date | Sep 15, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0818
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present disclosure discloses a digital phase locking loop and a method. The digital phase locking loop includes a trigger and a delay line. The trigger receives a delayed clock signal output by the delay line, and receives a signal of a selection end of a first delay element in the delay line; the selection end is in a gating state before triggering of the trigger. The trigger samples the signal of the selection end of the first delay element, and outputs the sampled signal to a selection end of a second delay element in the delay line; the selection end of the second delay element is in the gating state after triggering of the trigger. The signal of the selection end of the first delay element is sampled by the trigger, and the sampled result is used as the signal of the selection end of the second delay element, thus reducing glitches caused by transition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.