Antifuse programmable memory array
US8395923B2 · kind B2 · utility
8Cited by
19References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2009 |
| Grant date | Mar 12, 2013 |
| Priority date | — |
| Expiry date | Dec 13, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, such as PROM, OTPROM, and other such programmable non-volatile memories. The circuitry employs an antifuse scheme that includes an array of memory bitcells, each containing a program device and an antifuse element configured with current path isolation well and for storing the memory cell state. The bitcell configuration, which can be used in conjunction with column/row select circuitry, power selector circuitry, and/or readout circuitry, allows for high-density memory array circuit designs and layouts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.