Digital pulse width modulator
US8396111B2 · kind B2 · utility
4Cited by
5References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2010 |
| Grant date | Mar 12, 2013 |
| Priority date | — |
| Expiry date | Sep 23, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00156
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A DPWM (1) has a locked loop (4) which receives an input clock signal and provides an out-of-phase delayed clock at the output of each cell in the loop (35). A multiplexer (5) selects one of the cell outputs at any one time. This allows the DPWM (1) to have a greater resolution which would otherwise be achieved with the same input clock. The resolution is further increased using an interpolator. A programmable module (2) has a control block (20) which interfaces with external CPU and DSP hosts and transmits programmed parameters to finite state machine controllers (15), each providing an independent output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.