Efficient hardware scheme to support cross-cluster transactional memory
US8396937B1 · kind B1 · utility
20Cited by
19References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 30, 2007 |
| Grant date | Mar 12, 2013 |
| Priority date | — |
| Expiry date | Dec 28, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for increasing programmability and scalability of a multi-processor network. A system includes two or more nodes coupled via a network with each node comprising a processor unit and memory. The processor unit includes one or more processors and a wiretap unit. The wiretap unit is configured to monitor memory accesses of the processors. A transaction may execute a number of read and/or write operations to memory. The nodes are configured to replicate one or more portions of memory; detect data conflicts to memory; and restore memory to pre-transaction state if needed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.