Masked register write method and apparatus
US8397005B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2010 |
| Grant date | Mar 12, 2013 |
| Priority date | — |
| Expiry date | Jul 16, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hardware device register is written without transferring the register content from the hardware device to a host device over an interface bus for modification. The hardware device receives an address identifying the target register included in the hardware device and bit information associated with a write operation involving the target register from the host device over the interface bus. The address is stored in a first register included in the hardware device and dedicated for supporting write operations. The bit information is stored in a second register included in the hardware device and also dedicated for supporting write operations. The target register is accessed based on the address stored in the first register dedicated for supporting write operations and one or more bits of the target register are written based on the bit information without first transferring the register content to the host device over the interface bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.