System and method for cache coherency in a multiprocessor system
US8397029B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2007 |
| Grant date | Mar 12, 2013 |
| Priority date | — |
| Expiry date | Jun 5, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for maintaining cache coherency operates in a data processing system with a system memory and a plurality of processing units (PUs), each PU having a cache, and each PU coupled to at least another one of the plurality of PUs. A first PU receives a first data block for storage in a first cache of the first PU. The first PU stores the first data block in the first cache. The first PU assigns a first coherency state and a first tag to the first data block, wherein the first coherency state is one of a plurality of coherency states that indicate whether the first PU has accessed the first data block. The plurality of coherency states further indicate whether, in the event the first PU has not accessed the first data block, the first PU received the first data block from a neighboring PU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.