TLB prefetching
US8397049B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2009 |
| Grant date | Mar 12, 2013 |
| Priority date | — |
| Expiry date | Nov 14, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a memory management unit (MMU) is configured to retain a block of data that includes multiple page table entries. The MMU is configured to check the block in response to TLB misses, and to supply a translation from the block if the translation is found in the block without generating a memory read for the translation. In some embodiments, the MMU may also maintain a history of the TLB misses that have used translations from the block, and may generate a prefetch of a second block based on the history. For example, the history may be a list of the most recently used Q page table entries, and the history may show a pattern of access that are nearing an end of the block. In another embodiment, the history may comprise a count of the number of page table entries in the block that have been used.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.