Method and apparatus for securing digital information on an integrated circuit read only memory during test operating modes
US8397079B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2008 |
| Grant date | Mar 12, 2013 |
| Priority date | — |
| Expiry date | Nov 21, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318541
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The embodiments protect an IC against Design-For-Test (DFT) or other test mode attack. Secrets in ROM or PROM are secured. One embodiment for securing information on an IC includes receiving a ROM read command, writing data from a plurality of ROM address locations to an encryption logic in response to receiving the ROM read command, and writing an encryption logic output of the encryption logic to a test control logic, the encryption logic output representing the data from the plurality of ROM address locations. Writing the data from the plurality of ROM address locations to the encryption logic may also include writing the data from the plurality of ROM address locations to a multiple input shift register (MISR) in response to the ROM read command, and writing an MISR output to the test control logic, the MISR output representing the data from the plurality of ROM address locations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.