Circuits and methods for detection of soft errors in cache memories
US8397130B2 · kind B2 · utility
14Cited by
17References
28Claims
0Family size
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Key dates
| Filing date | Nov 25, 2009 |
| Grant date | Mar 12, 2013 |
| Priority date | — |
| Expiry date | Mar 24, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of circuits and methods for circuits for the detection of soft errors in cache memories are described herein. Other embodiments and related methods and examples are also described herein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.