Patent · US Active

Circuits and methods for dual redundant register files with error detection and correction mechanisms

US8397133B2 · kind B2 · utility

10Cited by
17References
25Claims
0Family size

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Key dates

Filing dateNov 25, 2009
Grant dateMar 12, 2013
Priority date—
Expiry dateFeb 23, 2031

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F12/1027
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

Embodiments of circuits and method for dual redundant register files with error detection and correction mechanisms are described herein. Other embodiments and related examples are also described herein.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.