Method of detecting an attack by fault injection on a memory device, and corresponding memory device
US8397152B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2010 |
| Grant date | Mar 12, 2013 |
| Priority date | — |
| Expiry date | Mar 3, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device may include a memory plane including a group of memory cells configured to store a block of bits including data bits and parity bits, and a detector for detecting a fault injection including a reader to read each bit, and a first checker to perform, when reading a block, a parity check based on the read value of each data and parity bit. The memory plane may include reference memory cells arranged between some of the memory cells to create packets of m memory cells. Each reference memory cell may store a reference bit and each packet of m memory cells may store m bits of the associated block, when m is greater than 1, with different parities. The detector may further include a second checker to perform, when reading the block, a check on the value of each reference bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.