Versatile method and tool for simulation of aged transistors
US8397199B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 2010 |
| Grant date | Mar 12, 2013 |
| Priority date | — |
| Expiry date | May 11, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, an aging analysis tool may be configured to identify transistors that are expected to experience aging effects according to worst case stress vectors and/or designer identified worst case conditions. The aging analysis tool may modify a representation of the circuit (e.g. a netlist), replacing the identified transistors with aged transistors (e.g. by modifying parameters of the transistors in the netlist). The aging analysis tool may process the modified netlist over a range of conditions at which the circuit is expected to operate, to ensure that the design meets specifications after aging. The process may be repeated until the aged design meets specifications (with circuit modifications made by the designer to improve the design).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.