Method for performing parallel stochastic assembly
US8399986B2 · kind B2 · utility
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28Claims
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Key dates
| Filing date | Mar 25, 2011 |
| Grant date | Mar 19, 2013 |
| Priority date | — |
| Expiry date | May 5, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/53178
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of positioning at least 2 chips simultaneously on a substrate by parallel stochastic assembly in a first liquid is disclosed. In one aspect, the chips are directed to target sites on the substrate within the first liquid. The target sites are covered with a second liquid. The second liquid and the first liquid are immiscible. The chips are attracting the first liquid. A predetermined surface is chosen or treated on each chip such that it is selectively attracted by the second liquid and attracting the first liquid.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.