Electrostatic discharge (ESD) protection circuits, integrated circuits, systems, and operating methods thereof
US8400742B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2010 |
| Grant date | Mar 19, 2013 |
| Priority date | — |
| Expiry date | Sep 15, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/046
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An electrostatic discharge (ESD) protection circuit coupled with an input/output (I/O) pad. The ESD protection circuit includes a clamp field effect transistor (FET) coupled between a first supply voltage and a second supply voltage. An inverter includes an input end and an output end. The output end of the inverter is coupled with a gate of the clamp FET. A RC time constant circuit is disposed between the first supply voltage and the second supply voltage. A current mirror includes a first transistor. The current mirror is coupled between the input end of the inverter and the second supply voltage. A circuit is coupled with the input end of the inverter. The circuit is capable of outputting a voltage state on the input end of the inverter that is capable of substantially turning off the clamp FET while the I/O pad is subjected to a latch-up test using a negative current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.