Adjustable impedance SRAM memory device
US8400820B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 21, 2010 |
| Grant date | Mar 19, 2013 |
| Priority date | — |
| Expiry date | Apr 5, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/412
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of a memory device includes a plurality of memory cells; each memory cell includes a latch adapted to store an information bit. Said latch includes a first logic gate including a first input terminal and a first output terminal and a second logic gate including a second input terminal and a second output terminal. Said first input terminal is connected to said second output terminal and said first output terminal is connected to said second input terminal. The memory device further includes reading and writing means adapted to perform a read operation or a write operation of the information bit. Said first logic gate includes a pull-up branch coupled between a terminal for providing a supply voltage and the first output terminal, and a pull-down branch coupled between the first output terminal and a terminal for providing a reference voltage. Said second logic gate includes a pull-up branch coupled between a terminal for providing the supply voltage and the second output terminal, and a pull-down branch coupled between the second output terminal and a terminal for providing the reference voltage. Said memory device includes variation means adapted to selectively vary …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.