Nonvolatile semiconductor memory device
US8400828B2 · kind B2 · utility
2Cited by
8References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 30, 2012 |
| Grant date | Mar 19, 2013 |
| Priority date | — |
| Expiry date | Mar 30, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B41/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A nonvolatile semiconductor memory device including a memory cell array of memory cells arranged in a matrix, each of which includes a selecting transistor and a memory cell transistor; a column decoder controlling the potential of bit lines; a voltage application circuit controlling the potential of the first word lines; a first row decoder controlling the potential of the second word lines; and a second row decoder controlling the potential of the source line. The column decoder is formed of a circuit whose withstand voltage is lower than the voltage application circuit and the second row decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.