E/P durability by using a sub-range of a full programming range
US8400834B2 · kind B2 · utility
1Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2011 |
| Grant date | Mar 19, 2013 |
| Priority date | — |
| Expiry date | Nov 14, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5646
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND Flash memory controller is used to perform an erase operation on a NAND Flash memory chip including to a cell on the NAND Flash memory chip; the cell is configured to store a first number of bits. It is determined whether the erase operation performed on the NAND Flash memory chip is successful. In the event it is determined that the erase operation performed on the NAND Flash memory chip is unsuccessful, the number of bits stored by the cell is reduced from the first number of bits to a second number of bits; the second number of bits is strictly less than the first number of bits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.