Column address strobe write latency (CWL) calibration in a memory system
US8400845B2 · kind B2 · utility
3Cited by
2References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2011 |
| Grant date | Mar 19, 2013 |
| Priority date | — |
| Expiry date | Apr 14, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Column address strobe write latency (CWL) calibration including a method for calibrating a memory system. The method includes entering a test mode at a memory device and measuring a CWL at the memory device. A difference between the measured CWL and a programmed CWL is calculated. The calculated difference is transmitted to a memory controller that uses the calculated difference for adjusting a timing delay to match the measured CWL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.