Bit line negative potential circuit and semiconductor storage device
US8400848B2 · kind B2 · utility
2Cited by
6References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 18, 2011 |
| Grant date | Mar 19, 2013 |
| Priority date | — |
| Expiry date | Aug 10, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a bit line negative potential circuit includes a bit line capacitance compensation capacitor which compensates the capacitance of a bit line and a peripheral capacitance compensation capacitor which compensates the peripheral capacitance of the bit line. After the bit line is switched to a low potential, the bit line is driven based on a charging voltage of the bit line capacitance compensation capacitor and the peripheral capacitance compensation capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.