Patent · US Active

Configurable memory block

US8400863B1 · kind B1 · utility

1Cited by

11References

20Claims

0Family size

Assignee

Altera Corporation · US

Inventors

Zun Yang Tan · Kuantan, MY
Wei Yee Koay · Kampung Bukit Kechil, MY
Boon Jin Ang · Butterworth, MY
Tat Mun Lui · Petaling Jaya, MY
Eu Geen Chew · Bayan Lepas, MY

Key dates

Filing date	Aug 20, 2010
Grant date	Mar 19, 2013
Priority date	—
Expiry date	Dec 31, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG11C8/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Circuits for a memory array and a method of operating a configurable memory block are disclosed. An embodiment of the disclosed memory circuits includes a first memory block coupled to a second memory block to form an array of memory blocks. Each of the memory blocks has multiple bit lines with a dedicated address decoder coupled to the bit lines from each of the memory blocks. Switches are placed in between the first and second memory blocks such that each of the bit lines from the first memory block is connected to a corresponding bitline from the second memory block through one of the switches. The switches may be used to either connect the second memory block to the first memory block or disconnect the second memory block from the first memory block.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.