Decision feedback equalization scheme with minimum correction delay
US8401063B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2009 |
| Grant date | Mar 19, 2013 |
| Priority date | — |
| Expiry date | Mar 27, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03579
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A decision feedback equalizer includes a correction circuit to correct a sampled value of an incoming bit based on intersymbol interference of at least one preceding bit, and to generate a received bit. The correction circuit includes a first multiplexer and a first pair of latches coupled thereto. The first multiplexer is controlled by a clock signal to generate a digital level representative of a sign of a first correction coefficient to be subtracted from the sampled value of the incoming bit for deleting the intersymbol interference. The first pair of latches receives as input the received bit and is clocked in phase opposition by the clock signal to generate respective latched replicas of the received bit during respective active phases of the clock signal. The respective latched replicas are input to the first multiplexer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.