Post-equalization amplitude latch-based channel characteristic measurement
US8401135B2 · kind B2 · utility
2Cited by
3References
12Claims
0Family size
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Key dates
| Filing date | Feb 2, 2010 |
| Grant date | Mar 19, 2013 |
| Priority date | — |
| Expiry date | Jul 20, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/14
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A serial data receiver includes an amplitude path including a first signal conditioner that adds a first offset or subtracts a second offset based on a selection input, a preamp configured to receive a signal from a transmitter and provide an input signal to the amplitude path, an amplitude latch coupled to the amplitude path, a data latch having a data output and a decision feedback equalization (DFE) logic block coupled to the first conditioning element and the data output and configured to generate the selection output based on the data output of the data latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.