Remapping of data addresses for large capacity low-latency random read memory
US8402247B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 7, 2012 |
| Grant date | Mar 19, 2013 |
| Priority date | — |
| Expiry date | Mar 7, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/651
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described herein are method and apparatus for using an LLRRM device as a storage device in a storage system. At least three levels of data structures may be used to remap storage system addresses to LLRRM addresses for read requests, whereby a first-level data structure is used to locate a second-level data structure corresponding to the storage system address, which is used to locate a third-level data structure corresponding to the storage system address. An LLRRM address may comprise a segment number determined from the second-level data structure and a page number determined from the third-level data structure. Update logs may be produced and stored for each new remapping caused by a write request. An update log may specify a change to be made to a particular data structure. The stored update logs may be performed on the data structures upon the occurrence of a predetermined event.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.