Method and apparatus to maximize power of a computer system for effective testing
US8402292B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2009 |
| Grant date | Mar 19, 2013 |
| Priority date | — |
| Expiry date | Feb 13, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Implementations of the present invention may involve methods and systems to improve the combined power consumption and thermal response of individual components of a computer system as the components are stressed concurrently during simulation or testing of the system. A group of operating system-level instruction sets for several individual components of the computer system may be designed to stress the components and executed concurrently while power and thermal measurements are taken. The instruction sets may utilize one or more software threads of the computer system or hardware threads such that minimal interference between components occurs as the system is tested. Further, the system components may be partitioned between separate instruction sets. By minimizing the interference between the components while the system is operating, a more accurate power consumption and thermal effect measurements may be taken on the computer system to better approximate the performance of the system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.