Protection of intellectual property cores through a design flow
US8402401B2 · kind B2 · utility
22Cited by
4References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2010 |
| Grant date | Mar 19, 2013 |
| Priority date | — |
| Expiry date | Nov 9, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/16
- WIPO fieldControl
- WIPO sectorInstruments
Abstract
One embodiment provides a method for protecting an integrated circuit chip design. The method can include storing in memory a circuit description of an integrated circuit core comprising a set of nodes and selecting a plurality of modification nodes from the set of nodes. A sequential structure can be inserted into the circuit description to provide a modified circuit description, the sequential structure utilizing the plurality of modification nodes as inputs. The modified circuit description can be stored in memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.