Semiconductor device and manufacturing method thereof
US8404547B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2009 |
| Grant date | Mar 26, 2013 |
| Priority date | — |
| Expiry date | Jul 9, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/256
Abstract
Provided is a manufacturing method for an offset MOS transistor capable of operating safely even under a voltage of 50 V or higher. In the offset MOS transistor which includes a LOCOS oxide film, the LOCOS oxide film formed in a periphery of a drain diffusion layer, in which a high withstanding voltage is required, is etched, and the drain diffusion layer is formed so as to spread into a surface region of a semiconductor substrate located below a region in which the LOCOS oxide film is thinned. As a result, end portions of the drain diffusion layer are covered by an offset diffusion layer, whereby electric field concentration occurring in a region of a lower portion of the drain diffusion layer can be relaxed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.