Method of manufacturing via electrode
US8404588B2 · kind B2 · utility
2Cited by
1References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2011 |
| Grant date | Mar 26, 2013 |
| Priority date | — |
| Expiry date | Oct 6, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a method of manufacturing a via electrode by which productivity and production yield can be augmented or maximized. The method of the present invention includes: forming a via hole at a substrate; forming a catalyst layer at a sidewall and a bottom of the via hole; and forming a graphene layer in the via hole by exposing the catalyst layer to a solution mixed with graphene particles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.