Semiconductor memory device

US8405142B2 · kind B2 · utility

Assignee

• Kabushiki Kaisha Toshiba · JP

Inventors

• Ryota Katsumata · Yokohama, JP
• Kazuyuki Higashi · Farmington Hills, US
• Yoshiaki Fukuzumi · Yokkaichi, JP

Key dates

• Filing date: Mar 9, 2011
• Grant date: Mar 26, 2013
• Expiry date: May 23, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/693

Abstract

According to one embodiment, a semiconductor memory device includes a substrate, a multilayer body, a semiconductor member and a charge storage layer. The multilayer body is provided on the substrate, with a plurality of insulating films and electrode films alternately stacked, and includes a first staircase and a second staircase opposed to each other. The semiconductor member is provided in the multilayer body outside a region provided with the first staircase and the second staircase, and the semiconductor member extends in stacking direction of the insulating films and the electrode films. The charge storage layer is provided between each of the electrode films and the semiconductor member. The each of the electrode films includes a first terrace formed in the first staircase, a second terrace formed in the second staircase and a bridge portion connecting the first terrace and the second terrace.