Bipolar integration without additional masking steps
US8405157B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 26, 2008 |
| Grant date | Mar 26, 2013 |
| Priority date | — |
| Expiry date | Jun 26, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/84
Abstract
The invention relates to a BiMOS semiconductor component having a semiconductor substrate wherein, in a first active region, a depletion-type MOS transistor is formed comprising additional source and drain doping regions of the first conductivity type extending in the downward direction past the depletion region into the body doping region while, in a second active region, (101), a bipolar transistor (100) is formed, the base of which comprises a body doping region (112) and the collector of which comprises a deep pan (110), wherein an emitter doping region (114) of the first conductivity type and a base connection doping region (118) of the second conductivity type are formed in the body doping region. The semiconductor element can be produced with a particularly low process expenditure because it uses the same basic structure for the doping regions in the bipolar transistor as are used in the MOS transistor of the same semiconductor component.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.