Thin film transistor array substrate and manufacturing method thereof
US8405234B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2011 |
| Grant date | Mar 26, 2013 |
| Priority date | — |
| Expiry date | Jul 14, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A thin film transistor (TFT) array substrate includes a substrate having a plurality of normal alignment regions, a plurality of abnormal alignment regions, and a device region defined thereon, a plurality of scan lines, a plurality of data lines, a plurality of storage electrode lines, and a plurality of switch devices positioned in the device region, a plurality of alignment structures positioned in the abnormal alignment regions, and an alignment layer formed on the substrate and the alignment structures. The alignment layer further includes a plurality of first alignment slits covering the alignment structures in the abnormal alignment regions and a plurality of second alignment slits in the normal alignment regions. A depth and a width of the second alignment slits are identical to a depth and a width of the first alignment slits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.