Output buffer with adjustable feedback
US8405424B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 8, 2011 |
| Grant date | Mar 26, 2013 |
| Priority date | — |
| Expiry date | Jun 8, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018571
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system according to one embodiment includes input stage circuitry configured to receive input data; output stage circuitry configured to generate buffered output data based on said received input data, said output stage circuitry comprising a first switch and a second switch, wherein said first switch comprises a first gate configured to control said first switch through an inverted gate signal and said second switch comprises a second gate configured to control said second switch through a non-inverted gate signal; first feedback inverter circuitry configured to enable pull-up of said second gate based on an input to said first gate, said first feedback inverter circuitry is further configured to provide an adjustable transition threshold for generation of said pull-up enable; and second feedback inverter circuitry configured to enable pull-down of said first gate based on an input to said second gate, said second feedback inverter circuitry is further configured to provide an adjustable transition threshold for generation of said pull-down enable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.