Read-only memory (ROM) bitcell, array, and architecture
US8406031B2 · kind B2 · utility
5Cited by
3References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Dec 16, 2010 |
| Grant date | Mar 26, 2013 |
| Priority date | — |
| Expiry date | Jan 26, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments provide improved memory bitcells, memory arrays, and memory architectures. In an embodiment, a memory cell comprises a transistor having drain, source, and gate terminals; and a plurality of program nodes, with each of the program nodes charged to a pre-determined voltage and coupled to a respective one of a plurality of bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.