Iterative demodulation and decoding for multi-page memory architecture
US8406051B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2010 |
| Grant date | Mar 26, 2013 |
| Priority date | — |
| Expiry date | May 20, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for accessing encoded data stored in a solid state non-volatile memory device include iteratively demodulating and decoding the data. The memory device includes memory cells arranged to store multiple bits of data per memory cell. The memory cells are capable of storing multiple pages of data. Each bit stored in a memory cell is associated with a page of data that is different from other pages associated with other bits stored in the memory cell. The multiple pages are demodulated responsive to sensed voltage levels of the memory cells, and a demodulated output is provided for each page of the multiple pages. A decoded output for each page of the multiple pages is generated. Decoding the page and demodulating the multiple pages proceeds iteratively, including an exchange of information between the decoder and the demodulator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.