Fast in-loop filtering in VC-1
US8406552B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2008 |
| Grant date | Mar 26, 2013 |
| Priority date | — |
| Expiry date | Jan 21, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/865
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method of filtering a pixels along a block edge during decoding of compressed VC-1 video includes loading edge segments with pixels along the sides of a block edge into registers, calculating a selection mask for a third pixel pair, and filtering the pixels in the edge segments simultaneously in the registers, if the selection mask meets a predetermined criteria. In another embodiment, a method of filtering pixels along a block edge during decoding of compressed VC-1 video includes loading edge segments with pixels along the side of a block edge into registers, swapping a first pair of the pixels with a second pair of the pixels, where each of the pairs of pixels are third pixel pairs of their respective segments, filtering the pairs of pixels simultaneously in the registers, and filtering the remaining pixels of the respective edge segments, if the results of filtering the third pixels pairs meet a predetermined criteria. The registers may be single instruction multiple data (SIMD) registers used with a Wireless MMX processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.