Method and system for improving serial port memory communication latency and reliability
US8407427B2 · kind B2 · utility
1Cited by
3References
36Claims
0Family size
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Key dates
| Filing date | Oct 23, 2009 |
| Grant date | Mar 26, 2013 |
| Priority date | — |
| Expiry date | Sep 22, 2031 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, apparatus and system for reducing memory latency is disclosed. In one embodiment, data between a host computer system and a memory is communicated via a port or a group of ports at the memory over multiple time intervals, wherein the host computer is coupled to the memory. Further, a command associated with the data is communicated between the host computer system and the memory via the port or the group of ports over a single time interval.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.