Serial bus clock frequency calibration system and method thereof
US8407508B2 · kind B2 · utility
5Cited by
6References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2010 |
| Grant date | Mar 26, 2013 |
| Priority date | — |
| Expiry date | Oct 13, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/10
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A serial bus clock frequency calibration system and a method thereof are disclosed herein. The system utilizes a first frequency calibration device, a second frequency calibration device and a third frequency calibration device to share the same oscillator as so to perform multi-stage clock frequency resolution calibrations for different frequency-tuning ranges. This can bring an optimal frequency resolution, greatly reduce system complexity and save element cost.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.