Controlling memory redundancy in a system
US8407516B2 · kind B2 · utility
8Cited by
10References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2009 |
| Grant date | Mar 26, 2013 |
| Priority date | — |
| Expiry date | Apr 29, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present invention provides an ability to handle an error occurring during a memory migration operation in a high availability system. In addition, a method can be used to dynamically remap a memory page stored in a non-mirrored memory region of memory to a mirrored memory region. This dynamic remapping may be responsive to a determination that the memory page has been accessed more than a threshold number of times, indicating a criticality of information on the page. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.