Graphical block-based design exploration tool
US8407645B1 · kind B1 · utility
9Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2009 |
| Grant date | Mar 26, 2013 |
| Priority date | — |
| Expiry date | Jun 12, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A graphical block-based design exploration tool displays multiple views of a chip design. These views may include a logical view, physical view, hierarchy view, and a timing display view, displayed side-by-side or sequentially with or without animation. Various entities and their relationships to each other are displayed in these different view arrangements to allow a user to quickly grasp the entire design and to perform design techniques such as partitioning and floor planning. The display properties are user configurable to organize the information based on user preferences.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.