Planarization method for high wafer topography
US8409456B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 2011 |
| Grant date | Apr 2, 2013 |
| Priority date | — |
| Expiry date | Oct 6, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31138
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for planarizing a semiconductor device includes providing a substrate having at least one opening therein, each opening defining a lower portion and an upper portion; coating a light sensitive material layer over the substrate, the light sensitive material layer covering the lower and upper portions of the at least one opening; etching back the light sensitive material layer to expose the upper portion of the at least one opening; repeating the steps of coating and etching to remove a predetermined amount below the upper portion of the at least one opening; depositing an insulating layer over the substrate; and planarizing the insulating layer until the upper portion of the at least one opening is exposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.