Low temperature wafer level processing for MEMS devices
US8409901B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 11, 2009 |
| Grant date | Apr 2, 2013 |
| Priority date | — |
| Expiry date | Mar 11, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1461
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Microelectromechanical systems (MEMS) are small integrated devices or systems that combine electrical and mechanical components. It would be beneficial for such MEMS devices to be integrated with silicon CMOS electronics and packaged in controlled environments and support industry standard mounting interconnections such as solder bump through the provisioning of through-wafer via-based electrical interconnections. However, the fragile nature of the MEMS devices, the requirement for vacuum, hermetic sealing, and stresses placed on metallization membranes are not present in packaging conventional CMOS electronics. Accordingly there is provided a means of reinforcing the through-wafer vias for such integrated MEMS-CMOS circuits by in filling a predetermined portion of the through-wafer electrical vias with low temperature deposited ceramic materials which are deposited at temperatures below 350° C., and potentially to below 250° C., thereby allowing the re-inforcing ceramic to be deposited after fabrication of the CMOS electronics.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.