Method of manufacturing transparent transistor with multi-layered structures
US8409935B2 · kind B2 · utility
6Cited by
2References
2Claims
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Key dates
| Filing date | Aug 21, 2012 |
| Grant date | Apr 2, 2013 |
| Priority date | — |
| Expiry date | Aug 21, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
Abstract
A method of manufacturing a transparent transistor including a substrate, source and drain electrodes formed on the substrate, each having a multi-layered structure of a lower transparent layer, a metal layer and an upper transparent layer, a channel formed between the source and drain electrodes, and a gate electrode aligned with the channel. The lower transparent layer or the upper transparent layer is formed of a transparent semiconductor layer, which is the same as the channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.