Non-volatile memory device including a stacked structure and voltage application portion
US8410540B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2010 |
| Grant date | Apr 2, 2013 |
| Priority date | — |
| Expiry date | Jun 9, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/77
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a non-volatile memory device includes a stacked structure including a memory portion and an electrode having a surface facing the memory portion; and a voltage application portion to apply a voltage to the memory portion to change resistance. The surface includes first and second regions. The first region contains a first nonmetallic element and at least one element of a metallic element, Si, Ga, and As. The second region contains a second nonmetallic element and the at least one element. The second region has a content ratio of the second nonmetallic element higher than that in the first region. A difference in electronegativity between the second nonmetallic element and the at least one element is greater than that between the first nonmetallic element and the at least one element. At least one of the first and second regions has an anisotropic shape.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.