Adder-embedded dynamic preamplifier
US8410972B2 · kind B2 · utility
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3References
18Claims
0Family size
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Key dates
| Filing date | Aug 4, 2011 |
| Grant date | Apr 2, 2013 |
| Priority date | — |
| Expiry date | Sep 8, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45392
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for an adder-embedded dynamic preamplifier system with dynamic comparator and current mode adder including differential switches for precharging, a switch for evaluation; and reference, feedfoward input sections. When differential switches are closed, OUTN and OUTP are precharged. During the evaluation, discharging currents are proportionately determined by input and reference values. A following latch amplifies the discharging differences of OUTN and OUTP.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.