Programmable read only memory
US8411482B2 · kind B2 · utility
3Cited by
5References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 20, 2008 |
| Grant date | Apr 2, 2013 |
| Priority date | — |
| Expiry date | Dec 14, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell includes a fuse and at least one transistor. The transistor is used to control the programming or sensing of the fuse. A program voltage is applied to a stack of first and second conductive layers. A first portion of the stack couples the program voltage to a terminal of the transistor in a cell. A second portion of the stack couples the program voltage to a terminal of the transistor in another cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.