Memory array with distributed clear transistors and variable memory element power supply
US8411491B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2011 |
| Grant date | Apr 2, 2013 |
| Priority date | — |
| Expiry date | May 19, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory elements may be provided that include bi-stable data storage elements based on cross-coupled inverters. A pair of address transistors may be used to implement a differential data writing scheme for the memory elements. One of the address transistors may be coupled between a first data line and a first data storage node in each memory element and another of the address transistors may be coupled between a second data line and a second data storage node. A read circuit may be coupled to the second data storage node. Clear transistors may be interspersed through the array. The clear transistors may help pull the data lines to desired voltages during clear operations. An adjustable power supply may supply a weakened power supply voltage to a pull-up clear transistor and to the first and second inverters during clear operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.