Memory cell having reduced circuit area
US8411516B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 9, 2011 |
| Grant date | Apr 2, 2013 |
| Priority date | — |
| Expiry date | Oct 13, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a memory cell having a reduced circuit area, which comprises a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor is coupled to a readline and controlled by a wordline. The second transistor is coupled between the first transistor and a low-voltage power supply. The third transistor is coupled to the second transistor and controlled by a bitline. The third transistor controls turn-on and cutoff of the second transistor. Besides, the fourth transistor is coupled to the third transistor and a writeline, and is controlled by the wordline. Thereby, according to the present invention, four transistors form a memory cell, and the objective of saving circuit area can be achieved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.