Memory controller and associated control method
US8412883B2 · kind B2 · utility
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16Claims
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Key dates
| Filing date | Dec 22, 2010 |
| Grant date | Apr 2, 2013 |
| Priority date | — |
| Expiry date | Oct 12, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller and an associated controlling method are provided. The memory controller is connected to a memory module, and includes a FIFO buffer for receiving valid data outputted from the memory module, a write pointer for indicating written data stored in the FIFO buffer, and a read pointer for indicating read data stored in the FIFO buffer. According to the controlling method, during a CAS latency of the memory module after a read command is generated, the value of the write pointer is controlled to have the same value as that of the read pointer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.